Eh, recording raw sensor data is one area that Flash kind of loses out currently. Streaming data doesn’t care too much about your seek latency and if you’re constantly writing GBs day in and day out you are one of the few people who would actually hit the flash write endurance limitations, especially on MLC and TLC flash.
Assuming your usage is one where you dump sensor data onto the drives 24/7 and a process comes in behind that searching for anomalies/compressing it way way down to be dumped into some offline archival storage.
We’re writing digitized radio signal data to fill up a drive, then mailing the full drive to MIT to get correlated with data from telescopes on other continents. So flash would work just fine, given a reasonable file structure, like none at all. The original medium was magnetic tape on mile-long glass reels.
Sure, but so does clock skew. There’s a reason many of the traces around the RAM on motherboards are squiggly in shape - they need to all be the same length so parallel signals reach the RAM controller at the same time!
Just because we can make things smaller doesn’t mean we have to.
At some point there should be two development tracks – one for equipment that we’re supposed to be able to install with our bare hands, and the other for microscopes and tweezers. We’re already at a point that hobbyists can’t take anything apart anymore without a 50/50 risk of bricking our toys.
The Cray computers had all the cables cut to the same length, to ensure the same number of nanoseconds of delay on all, to make the logic design consistent.
I fully expect RAM to start using serial lanes like PCIe pretty soon. The high sped parallel data bus is moribund.
There was the rather more successful FBDIMM for large memory systems in the DDR2 era(sacrificed latency by tacking a little serializer/deserializer onto each DIMM; but unlike RDRAM could be produced out of industry standard DDR2 chips); but the idea seems to have had a bit of a hard life, especially given that “what if we got rid of that really fast, really wide, parallel multidrop bus?” seems like the sort of question that would attract enthusiastic answers.
There was also an attempt to meet halfway: Intel had their ‘Scalable memory buffers’ that acted as a standard memory controller for a few DIMMs but were connected to the CPU by a fast 'n narrow serial bus. AMD was going to have a similar thing, with the ‘socket G3 memory extender’; but that didn’t survive the cancellation of socket G3.
I suspect that people much smarter than me have their reasons; but while attempts to improve bus etiquette are very much a thing(with LRDIMMs); attempts to serialize it seem to actually have declined somewhat. RDRAM…didn’t set the world on fire…AMD never made it to G3; and while you might still be able to get the Intel memory buffers; it’s because they shipped with some of the fancy expensive Xeons with relatively long platform lives, not because they’ve continued iterating past Jordan Creek 2.
