I’ll be interested to see what people discover about the implementation of choosing one of two totally separate pairs of CPUs when they pop the top off.
Is there a nontrivial amount of peripheral duplication; or some sort of correspondingly smaller variant of scheme they used on the pi 5 to put basically all the peripherals on a single PCIe link from the BCM SoC?
I assume that hardware inspection will provide no insight into this; but I’d also be curious whose use cases were behind the substantial increase in platform lockdown features vs. the 2040. Secure and encrypted boot, anti-rollback, debug disable, glitch detection, and ‘trustzone’ isolation must have had someone’s interest to be worth the implementation.
