Definitely read his blog, too: Second IC :) – Sam Zeloof
From the video everything is used in sub-milliliter sized quantities. He’s applying small drops to the wafers, not soaking them in baths.
He says he’s trying to limit the dangerous chemicals and processes as much as possible.
First off, from the look of the Owsley Stanley dancing “Bear” on the chip it would be assumed he knows how to be safe um… ahem… ugh. Yeah!
So can I have what he’s having bartender???
Good on em for the having the abilty, MAN.
Not exactly. It’s not like he etched a thousand transistors all on a single chip. He has only 100 transistors per mask, which he exposed 12 separate times on that particular wafer. Had this been a commercial chip, the next step would be to saw the wafer into individual chips.
He tested each array of 100 and found at least one with no defects, and two with yields above 80%, which made him quite happy. As it should. So he knows his garage process is good on small chips, but probably not quite there to scale up to a larger chip yet. Yet.
I’m not saying this to take anything away from his accomplishments! His transistor density is on par with early CPU chips, which is completely awesome. But his yield is not a thousand per chip.
A kid in his garage.
Only a matter of time before 3D printing gets down micron-level accuracy, at which point the government (backed by Big Silicon) will step in and confiscate 3D printed chips.
Yep. If you have fab facility about the 1 micron mark, these are good for making little mechanical MEMS things. I wanted my company at the time to get one in the nineties. It would have been about half a million at the time, if we could have found one. That’s not doing it yourself, but it is also fun.
Oh man - that HP4145A SPA test rig gave me the chills - I worked 12 hour day/night shifts in a characterisation lab for GEC Plessey in the early 90’s - this was the obsolete tool to be avoided even then!
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